Integrated circuits (ICs) employ capacitors for charge storage purposes. For example, memory devices, including random access memories (RAMs) such as dynamic RAMs (DRAMs) store a charge in a capacitor. The level of the charge ("0" or "1") in the capacitor represents a bit of data.
A DRAM IC includes an array of memory cells interconnected by rows and columns. Typically, the row and column connections are referred to as wordlines and bitlines, respectively. Reading data from or writing data to the memory cells is accomplished by activating the appropriate wordlines and bitlines.
Typically, a DRAM memory cell comprises a metal oxide semiconductor field effect transistor (MOSFET) connected to a capacitor. The transistor includes a gate and first and second diffusion regions. The first and second diffusion regions are referred to either as the drain or source, respectively, depending on the operation of the transistor. For convenience, the terms drain and source are interchangeable. The gate of the transistor is coupled to a wordline, and the source is coupled to a bitline. The drain of the transistor is coupled to the capacitor or storage node. Applying the appropriate voltage to the gate switches on the transistor, forming a conductive path to the capacitor. This conductive path is closed when the transistor is switched off.
Trench capacitors are commonly employed in DRAMs. A trench capacitor is a three-dimensional structure formed into the silicon substrate. A conventional trench capacitor comprises a trench etched into the substrate. The trench is typically filled with n+ doped poly which serves as one plate of the capacitor (referred to as the storage node). The second plate of the capacitor, referred to as a "buried plate," is formed by, for example, outdiffusing n+ dopants from a dopant source into a region of the substrate surrounding the lower portion of the trench. A dielectric layer is provided to separate the two plates forming the capacitor. To prevent or reduce parasitic leakage that occurs along the upper portion of the trench to an acceptable level, an oxide collar of sufficient thickness is provided therein. Typically, the oxide collar is sufficiently thick to reduce the parasitic leakage to less than 1 fA/cell.
Continued demand to shrink devices has facilitated the design of DRAMs with greater density and smaller feature size and cell area. For example, design rules have been scaled from 0.25 microns (um) down to about 0.12 nm and below. At the smaller groundrules, the control of vertical parasitic MOSFET leakage between the storage node diffusion and the buried-plate becomes problematic due to the smaller trench dimension. This is because a smaller trench opening necessitates a corresponding reduction in collar thickness to facilitate filling of the trench. However, to reduce the parasitic leakage to below an acceptable level, the thickness of the collar needs to be about 25-70 nm, depending on operating voltage conditions. Such a thick collar hinders the filling of the smaller trench.
Another technique of reducing parasitic leakage is to increase dopant concentration of the well of the transistor. However, raising the dopant concentration increases the electric fields in the depletion regions, which results in a sharp increase in junction leakage. This is especially true when crystallographic defects are present in the silicon.
From the above discussion, it is desirable to provide a small trench capacitor with sufficiently low parasitic leakage.